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AIC1571
5-bit DAC, Synchronous PWM Power Regulator with Dual Linear Controllers
FEATURES
Provides 3 Regulated Voltages for Microprocessor Core, Clock and GTL Power. Simple Voltage-Mode PWM Control. Dual N-Channel MOSFET Synchronous Driver. Operates from +3.3V, +5V and +12V Inputs. Fast Transient Response. Full 0% to 100% Duty Ratios. 1.0% Output Voltage for VCORE and 2.0% Output Voltage Reference for VCLK and VGTL. TTL Compatible 5-bit Digital-to-Analog Core Output Voltage Selection. Range from 1.3V to 3.5V. 0.1V Steps from 2.1V to 3.5V. 0.05V Steps from 1.3V to 2.05V. Adjustable Current Limit without External Sense Resistor. Microprocessor Core Voltage Protection against Shorted MOSFET. Power Good Output Voltage Monitor. Over-Voltage and Over-Current Fault Monitors. 200KHz Free-Running Oscillator Programmable up to 350KHz.
DESCRIPTION
The AIC1571 combines a synchronous voltage mode controller with two linear controllers as well as the monitoring and protection functions in this chip. The PWM controller regulates the microprocessor core voltage with a synchronous rectified buck converter. One linear controller regulates power for the GTL bus and the other linear controller provides power for the clock driver circuit or memory (1.8V) An integrated 5 bit D/A converter that adjusts the core PWM output voltage from 2.1V to 3.5V in 0.1V increments and from 1.3V to 2.05V in 0.05V increments. The linear regulator uses an internal driver device to provide 2.5V2.5%. The linear controller drives with an external N-channel MOSEFET to provide 1.5V2.5%. This chip monitors all the output voltages. Power Good signal is issued when the core voltage is within 10% of the DAC setting and the other levels are above their under-voltage levels. Over-voltage protection for the core output uses the lower Nchannel MOSFET to prevent output voltage above 115% of the DAC setting. The PWM over-current function monitors the output current by using the voltage drop across the upper MOSFET's RDS(on), eliminating the need for a current sensing resistor.
APPLICATIONS
Full Motherboard Power Regulation for Computers. Power Integrations for 3 Output Power System.
Analog Integrations Corporation DS-1571-00 Oct 9, 00
4F, 9, Industry E. 9th Rd, Science Based Industrial Park, Hsinchu Taiwan, ROC TEL: 886-3-5772500 FAX: 886-3-5772510
www.analog.com.tw
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AIC1571
ORDERING INFORMATION
AIC1571-CX
PACKAGING TYPE S: SMALL OUTLINE
ORDER NUMBER
AIC1571CS (SO24)
PIN CONFIGURATION
VCC 1 VID4 2 VID3 3 VID2 4 VID1 5 VID0 6 PGOOD 7 24 UGATE 23 PHASE 22 LGATE 21 PGND 20 OCSET 19 VSEN 18 FB1 17 COMP1 16 FB3 15 GATE3 14 GND 13 GATE2
FAULT 8 SS 9 RT 10 FB2 11 VIN2 12
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC ........................................................................................ +15V .................................. GND -0.3V to VCC +0.3V ........................................................ GND -0.3V to 7V PGOOD, FAULT and GATE Voltage Input, Output , or I/O Voltage
Recommended Operating Conditions Supply Voltage; VCC ........................................... +12V10% Ambient temperature Range ........................................ 0C~70C Junction Temperature Range ....................................... 0C~100C Thermal Information Thermal Resistance, JA SOIC package ........................................................... 100C/W 2 SOIC package (with 3in of copper) .................................. 90C/W Maximum Junction Temperature (Plastic Package) ................................ 150C Maximum Storage Temperature Range ..................................... -65C ~ 150C Maximum Lead Temperature (Soldering 10 sec) ................................... 300C
TEST CIRCUIT
Refer to APPLICATION CIRCUIT.
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AIC1571
ELECTRICAL CHARACTERISTICS
fied) PARAMETER
VCC SUPPLY CURRENT Supply Current POWER ON RESET Rising VCC Threshold Falling VCC Threshold Rising VIN2 Under-Voltage Threshold VIN2 Under-Voltage Hysteresis Rising VOCSET1 Threshold OSCILLATOR Free Running Frequency Ramp. Amplitude REFERENCE AND DAC DAC (VID0~VID4) Input Low Voltage DAC (VID0~VID4) Input High Voltage DACOUT Voltage Accuracy FB2 Reference Voltage FB3 Reference Voltage VDAC=1.3V~3.5V VREF2 VREF3 VIDL VIDH 2 -1.0 1.245 1.250 1.270 1.275 +1.0 1.295 1.300 0.8 V V % V V RT=Open RT=open F VOSC 170 200 1.3 230 KHz VP-P VOCSET=4.5V VOCSET=4.5V VCCTHR VCCTHF VIN2THR VIN2HYS VOCSETH 8.6 8.2 2.5 9.5 9.2 2.6 130 1.3 10.4 10.2 2.7 V V V mV V UGATE, LGATE, GATE2 and GATE3 open ICC 1.8 5 mA
(Vcc=12V, TJ=25C, Unless otherwise speci SYMBOL MIN. TYP. MAX. UNIT
TEST CONDITIONS
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AIC1571
ELECTRICAL CHARACTERISTICS
PARAMETER LINEAR CONTROLLER Regulation Under-Voltage Level 0 < IGATE2/3 < 10mA FB2/3 falling FB2/3UV -2.5 70 +2.5 80 % % TEST CONDITIONS
(Continued)
SYMBOL MIN. TYP. MAX. UNIT
PWM CONTROLLER ERROR AMPLIFIER DC GAIN Gain Bandwidth Product Slew Rate COMP1=10pF GBWP SR 76 11 6 dB MHz V/S
PWM CONTROLLER GATE DRIVER Upper Drive Source Upper Drive Sink Lower Drive Source Lower Drive Sink PROTECTION VOUT1 Voltage Over-Voltage Trip OCSET Current Source FAULT Sourcing Current Soft-Start Current Chip Shutdown Soft Start Threshold POWER GOOD VOUT1 Upper Threshold VOUT1 Under-Voltage VOUT1 Hysteresis (VSEN/DACOUT) PGOOD Voltage Low VSEN Rising VSEN Falling Upper and Lower Threshold IPGOOD=-4mA VPGOOD 109 90.5 110.5 92 3 0.5 112 93.5 % % % V VSEN Rising VOCSET=4.5VDC VFAULT=10V OVP IOCSET IOVP ISS 112 170 10 115 200 16 11 1.0 118 230 % A mA A V VCC=12V, VUGATE=11V VCC=12V, VUGATE =1V VCC=12V, VLGATE=11V VCC=12V, VLGATE=1V RUGH RUGL RLGH RLGL 5.2 3.3 4.1 3 6.5 5 6 5
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AIC1571
TYPICAL PERFORMANCE CHARACTERISTICS
UGATE
UGATE
LGATE
LGATE
FIG.1 The gate drive waveforms
60
50
CUGATE=CLGATE=CGATE VCC=12V CGATE=5000pF
10000
40
Resistance (k)
1000
ICC (mA)
RT Pull Up to +12V
100
RT Pull Down to GND
30
CGATE=2000pF
20
10
CGATE=660pF
10
0 100
150
200
250
300
350
400
1 100
150
200
250
300
350
400
450
Switching Frequency (KHz)
Switching Frequency (KHz)
FIG. 2 Bias Supply Current VS. Frequency
FIG. 3 RT Resistance VS. Frequency
PGOOD (5V/div)
SS (2V/div)
PGOOD (5V/div) PGOOD (5V/div)
VOUT1 (1V/div)
SS (2V/div) SS (2V/div)
VOUT2 (1V/div) VOUT3 (1V/div)
VOUT2 (1V/div)
VOUT3
VOUT3
SS (2V/div)
VOUT1 (1V/div)
VOUT1 (1V/div)
FIG.4-1 Circuit 1---Soft Start Interval with 3 Outputs and PGOOD
FIG.4-2 Circuit 2---Soft Start Interval with 3 Outputs and PGOOD
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AIC1571
TYPICAL PERFORMANCE CHARACTERISTICS
(CONTINUED)
SS
FAULT
VDAC=3.5V
SS
VDAC=2V
Over Load Applied Inductor Current 10A/div
VDAC=1.3V
FIG. 5 Soft Start Initiates PWM Output
FIG. 6 Over-Current Operation on Inductor
VOUT1
VOUT3 (2mV/div)
2.0VDC
5A to 12A Load Step
1A to 2A Load Step
FIG. 7 Transient Response of PWM Output
FIG. 8 Transient Response of Linear Controller
90 80 70
100
DACOUT=2.0V TA=25C
95 90
Power MOSFET : CEB6030L Vo=2.8V
Number of Parts
Efficiency (%)
60 50 40 30 20 10 0 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
85 80 75 70 65
VIN=5V Switching Frequency = 200KHz
0 2 4 6 8 10 12
Vo=2V
Vo=1.3V
14 16 18 20
FIG. 9 DACOUT Voltage Accuracy (%)
FIG.10 Efficiency vs. Load Current (A)
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AIC1571
TYPICAL PERFORMANCE CHARACTERISTICS
220 215
0.8 0.6
(CONTINUED)
Switching Frequency (KHz)
210 205 200 195 190 185 180 -20 0 20 40 60 80 100
DACOUT Voltage Drift (%)
DACOUT=2.0V
0.4 0.2 0.0 -0.2 -0.4 -0.6 -20 -10 0
RT=OPEN
10
20
30
40
50
60
70
80
90 100
FIG.11 Oscillator Frequency vs. Temperature (C)
FIG.12 Temperature Drift of 24 Different Parts
210 205 200 195 190 185 180 -20
9.55
9.50
SS Charge Current (uA)
0 20 40 60 80
OCSET Current (A)
9.45
9.40
9.35
9.30
100
9.25 -20 -10
0
10
20
30
40
50
60
70
80
90
100
FIG.13 OCSET Current vs.Temperature (C)
1.0
FIG.14 SS Current vs. Temperature (C)
0.3
0.5
VCORE Drift Voltage (mV)
DACOUT=2.0V VIN=5V NO LOAD
0.2
NO LOAD
0.0
Vcore Drift (mV)
0.1
-0.5
0.0
-1.0
-1.5
-0.1
-2.0 10
11
12
13
14
15
16
17
18
-0.2 4.0
4.5
5.0
5.5
6.0
6.5
7.0
FIG.15 Vcore Drift vs. VCC (V)
FIG.16 Vcore Drift vs. VIN (V)
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AIC1571
BLOCK DIAGRAM
VSEN PGOOD VCC
FB3 + GATE3 + 0.3V GATE2 FB2 + 1.26V
VCC VIN2 OCSET INHiBIT
110% +
+ POWER ON RESET LUV
90%
OCSET + 200A
115%
+
OC1
+
PHASE VCC
VIN2 VCC FAULT SOFT START 10A
70K
FAULT LOGIC & LATCH
OV
UGATE
OFF
+ + ERROR AMP
PWM COMP
GATE CONTROL
5 BIT TTL D/A CONVERTER (DAC)
VCC LGATE
OSCILLATOR
PGND GND
4V
5V
70K 70K 70K 70K
SS
VID0 VID1 VID2 VID3 VID4
FB1
COMP1
RT
PIN DESCRIPTIONS
Pin 1: VCC: The chip power supply pin. It also provides the gate bias charge for all the MOSFETs controlled by the IC. Recommended supply voltage is 12V. Table 1 specifies the VDAC voltage for the 32 combinations of DAC inputs. Pin 7: PGOOD: Power good indicator pin. PGOOD is an open drain output. This pin is pulled low when the converter output is 10% out of the VDAC reference voltage and the other outputs are below their under-voltage thresholds. The PGOOD output is open for VID codes that inhibit operation. See Table 1. This pin is low during normal operation, but it is pulled to VCC in the event of an over-voltage or over-current condition.
Pin 2: Pin 3: Pin 4: Pin 5: Pin 6:
VID4: VID3: VID2: VID1: VID0:
5bit DAC voltage select pin. TTL inputs used to set the internal voltage reference VDAC. When left open, these pins are internally pulled up to 5V and provide logic ones. The level of VDAC sets the converter output voltage as well as the PGOOD and OVP thresholds.
Pin 8: FAULT:
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AIC1571
Pin 9: SS: Soft-start pin. Connect a capacitor from this pin to ground. This capacitor, along with an internal 10A (typically) current source, sets the soft-start interval of the converter. Pulling this pin low will shut down the IC. Frequency adjustment pin. Connecting a resistor (RT) from this pin to GND, increasing the frequency. Connecting a resistor (RT) from this pin to VCC, decreasing the frequency by the following figure (Fig.3). Connect this pin to a resistor divider to set the linear controller output voltage. This pin is used to monitor the 3.3V supply. If, following a startup cycle, the voltage drops below 2.6V (typically), the chip shuts down. A new soft-start cycle is initiated upon return of the 3.3V supply above the undervoltage threshold. An RC network is connected to FB1 in to compensate the voltage control feedback loop of the converter. Pin 18: FB1: The error amplifier inverting input pin. the FB1 pin and COMP1 pin are used to compensate the voltage-control feedback loop. Converter output voltage sense pin. Connect this pin to the converter output. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for over-voltage protection function.
Pin 10: RT:
Pin 19: VSEN:
Pin 11: FB2:
Pin 12: VIN2:
Pin 20: OCSET: Current limit sense pin. Connect a resistor ROCSET from this pin to the drain of the external highside N-MOSFET. ROCSET, an internal 200A current source (IOCSET), and the upper NMOSFET on-resistance (RDS(ON)) set the over-current trip point according to the following equation:
Pin 13: GATE2: Linear Controller output drive pin. This pin can drive either a Darlington NPN transistor or a Nchannel MOSFET. Pin 14: GND: Signal GND for IC. All voltage levels are measured with respect to this pin.
IPEAK =
Pin 21: PGND:
IOCSET x ROCSET RDS(ON)
Driver power GND pin. PGND should be connected to a low impedance ground plane in close to lower N-MOSFET source.
Pin 15: GATE3: Linear Controller output drive pin. This pin can drive either a Darlington NPN transistor or a Nchannel MOSFET. Pin 16: FB3: Negative feedback pin for the linear controller error amplifier connect this pin to a resistor divider to set the linear controller output voltage.
Pin 22: LGATE: Lower N-MOSFET gate drive pin. Pin 23: PHASE: Over-current detection pin. Connect the PHASE pin to source of the external high-side NMOSFET. This pin detects the voltage drop across the highside N-MOSFET RDS(ON) for over-current protection. Pin 24: UGATE: External high-side N-MOSFET gate drive pin. Connect UGATE to gate of the external high-side N-MOSFET.
Pin 17: COMP1: External compensation pin. This pin is connected to error amplifier output and PWM comparator.
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AIC1571
DESCRIPTION
The AIC1571 is designed for microprocessor computer applications with 3.3V and 5V power, and 12V bias input. This IC has one PWM controller and two linear controllers. The PWM controller is designed to regulate the microprocessor core voltage (VOUT1) by driving 2 MOSFETs (Q1 and Q2) in a synchronous rectified buck converter configuration. The core voltage is regulated to a level programmed by the 5 bit D/A converter. One integrated linear controller supplies the 2.5V clock power (VOUT2). The other linear controller drive an external MOSFET(Q3) to supply the GTL bus power(VOUT3) The Power-On Reset (POR) function continually monitors the input supply voltage +12V at VCC pin, the 5V input voltage at OCSET pin, and the 3.3V input at VIN2 pin. The POR function initiates soft-start operation after all three input supply voltage exceed their POR thresholds. Soft-Start The POR function initiates the soft-start sequence. Initially, the voltage on SS pin rapidly increases to approximate 1V. Then an internal 10A current source charges an external capacitor (CSS) on the SS pin to 4V. As the SS pin voltage slews from 1V to 4V, the PWM error amplifier reference input (Non-inverting terminal) and output (COMP1 pin) is clamped to a level proportional to the SS pin voltage. As the SS pin voltage slew from 1V to 4V, the output clamp generates PHASE pulses of increasing width that charge the output capacitors. Additionally both linear regulator's reference inputs are clamped to a voltage proportional to the SS pin voltage. This method provides a controlled output voltage smooth rise. Fig.4 and Fig.5 show the soft-start sequence for the typical application. The internal oscillator's triangular waveform is compared to the clamped error amplifier output voltage. As the SS pin voltage increases, the pulse width on PHASE pin increases. The interval of increasing pulse width continues until output reaches sufficient voltage to transfer control to the input reference clamp. Each linear output (VOUT2 and VOUT3) initially follows a ramp. When each output reaches sufficient voltage the input reference clamp slows the rate of output voltage rise. The PGOOD signal toggles `high' when all output voltage levels have exceeded their undervoltage levels. Fault Protection All three outputs are monitored and protected against extreme overload. A sustained overload on any output or over-voltage on PWM output disable all converters and drive the FAULT pin to VCC.
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AIC1571
OVER CURRENT LATCH LUV OC1 0.2V SS + 3.6V OV POR + S R Q
INHIBIT
S COUNTER R
FAULT LATCH S R Q FAULT VCC
Fig. 17 Simplified Schematic of Fault Logic A simplified schematic is shown in figure 17. An over-voltage detected on VSEN immediately sets the fault latch. A sequence of three overcurrent fault signals also sets the fault latch. An under-voltage event on either linear output (FB2 or FB3) is ignored until the soft-start interval. Cycling the bias input voltage (+12V) off then on reset the counter and the fault latch. Over-Voltage Protection During operation, a short on the upper PWM MOSFET (Q1) causes VOUT1 to increase. When the output exceed the over-voltage threshold of 115% of DACOUT, the FAULT pin is set to fault latch and turns Q2 on as required in order to regulate VOUT1 to 115% of DACOUT. The fault latch raises the FAULT pin close to VCC potential. A separate over-voltage circuit provides protection during the initial application of power. For voltage on VCC pin below the power-on reset (and above 4V), should VSEN exceed 0.7V, the lower MOSFET (Q2) is driven on as needed to regulate VOUT1 to 0.7V. Over-Current Protection All outputs are protected against excessive over-current. The PWM controller uses upper MOSFET's on-resistance, RDS(ON) to monitor the current for protection against shorted outputs. Both the linear regulator and controller monitor FB2 and FB3 for under-voltage to protect against excessive current. When the voltage across Q1 (ID*RDS(ON)) exceeds the level (200A*ROCSET), this signal inhibit all outputs. Discharge soft-start capacitor (Css) with 10A current sink, and increments the counter. Css recharges and initiates a softstart cycle again until the counter increments to 3. This sets the fault latch to disable all outputs. Fig. 6 illustrates the over-current protection until an over load on OUT1. Should excessive current cause FB2 or FB3 to fall below the linear under-voltage threshold, the LUV signal sets the over-current latch if Css is fully charged. Cycling the bias input power off then on reset the counter and the fault latch. The over-current function for PWM controller will trip at a peak inductor current (IPEAK) determined by:
IPEAK =
IOCSET x ROCSET RDS(ON)
The OC trip point varies with MOSFET's temperature. To avoid over-current tripping in the normal operating load range, determine the ROCSET resistor from the equation above with: 1. The maximum RDS(ON) at the highest junction. 2. The minimum IOCSET from the specification
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AIC1571
table. 3. Determine IPEAK > IOUT(MAX) + (inductor ripple current) /2. PWM OUT1 Voltage Program The output voltage of the PWM converter is programmed to discrete levels between 1.3V to 3.5V. The VID pins program an internal voltage reference (DACOUT) through a TTL compatible 5 bit digital to analog converter. The VID pins can be left open for a logic 1 input, because they are internally pulled up to 5V by a 70k resistor. Changing the VID inputs during operation is not recommended. All VID pin combinations resulting in an INHIBIT disable the IC and the open collector at the PGOOD pin. Shutdown Holding the SS pin low with an open drain or collector signal turns off all three regulators. The VID codes resulting in an INHIBIT as shown in Table 1 also shut down the IC. Table 1 VOUT1 Voltage Program (0=connected to GND, 1=open or connected to 5V) PIN NAME VID3 VID2 VID1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 0 0 0 1 1 0 1 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 For all package version PIN NAME DACOUT VOLTAGE VID4 VID3 VID2 VID1 1.30V 1 1 1 1 1.35V 1 1 1 1 1.40V 1 1 1 0 1.45V 1 1 1 0 1.50V 1 1 0 1 1.55V 1 1 0 1 1.60V 1 1 0 0 1.65V 1 1 0 0 1.70V 1 0 1 1 1.75V 1 0 1 1 1.80 V 1 0 1 0 1.85 V 1 0 1 0 1.90 V 1 0 0 1 1.95 V 1 0 0 1 2.00 V 1 0 0 0 2.05 V 1 0 0 0 DACOUT VOLTAGE INHIBIT 2.1 V 2.2 V 2.3 V 2.4 V 2.5 V 2.6 V 2.7 V 2.8 V 2.9 V 3.0 V 3.1 V 3.2 V 3.3 V 3.4 V 3.5 V
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Layout Considerations Any inductance in the switched current path generates a large voltage spike during the
switching interval. The voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress. Careful
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AIC1571
component selection and tight layout of critical components, and short, wide metal trace minimize the voltage spike. 1) A ground plane should be used. Locate the input capacitors (CIN) close to the power switches. Minimize the loop formed by CIN, the upper MOSFET (Q1) and the lower MOSFET (Q2) as possible. Connections should be as wide as short as possible to minimize loop inductance. 2) The connection between Q1, Q2 and output inductor should be as wide as short as practical. Since this connection has fast voltage transitions will easily induce EMI. 3) The output capacitor (COUT) should be located as close the load as possible. Because minimize the transient load magnitude for high slew rate requires low inductance and resistance in circuit board 4) The AIC1571 is best placed over a quiet ground plane area. The GND pin should be
+12V +
connected to the groundside of the output capacitors. Under no circumstances should GND be returned to a ground inside the CIN, Q1, Q2 loop. The GND and PGND pins should be shorted right at the IC. This help to minimize internal ground disturbances in the IC and prevents differences in ground potential from disrupting internal circuit operation. 5) The wiring traces from the control IC to the MOSFET gate and source should be sized to carry 1A current. Locate COUT2 close to the AIC1571 IC. 6) The Vcc pin should be decoupled directly to GND by a 1uF ceramic capacitor, trace lengths should be as short as possible.
VCC +3.3VIN + Q3 VOUT3 + COUT3 GATE3 VIN2
GND OCSET UGATE Q1 PHASE LOUT +
+5VIN
CIN
VOUT +
LGATE Q2 Q4 GATE2 SS VOUT2 + COUT2 Power Plane Layer Circuit Plane Layer Via Connection to Ground Plane Css PGND
COUT
Fig. 18 Printed circuit board power planes and islands A multi-layer printed circuit board is recommended. Figure 18 shows the connections of the critical components in the converter. The CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer.
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AIC1571
PWM Output Capacitors The load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demand. The ESR (equivalent series resistance) and ESL (equivalent series inductance) parameters rather than actual capacitance determine the buck capacitor values. For a given transient load magnitude, the output voltage transient change due to the output capacitor can be note by the following equation: Peak current in the inductor will be equal to the maximum output load current plus half of inductor ripple current. The ripple current is approximately equal to:
IRIPPLE =
(VIN - VOUT) x VOUT ; f x L x VIN
VOUT = ESR x IOUT + ESL x
IOUT is transient load current step.
IOUT , where T
f = AIC1571 oscillator frequency. The inductor must be able to withstand peak current without saturation, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss Input Capacitor Selection Most of the input supply current is supplied by the input bypass capacitor, the resulting RMS current flow in the input capacitor will heat it up. Use a mix of input bulk capacitors to control the voltage overshoot across the upper MOSFET. The ceramic capacitance for the high frequency decoupling should be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedance. The buck capacitors to supply the RMS current is approximate equal to:
After the initial transient, the ESL dependent term drops off. Because the strong relationship between output capacitor ESR and output load transient, the output capacitor is usually chosen for ESR, not for capacitance value. A capacitor with suitable ESR will usually have a larger capacitance value than is needed for energy storage. A common way to lower ESR and raise ripple current capability is to parallel several capacitors. In most case, multiple electrolytic capacitors of small case size are better than a single large case capacitor. Output Inductor Selection Inductor value and type should be chosen based on output slew rate requirement, output ripple requirement and expected peak current. Inductor value is primarily controlled by the required current response time. The AIC1571 will provide either 0% or 100% duty cycle in response to a load transient. The response time to a transient is different for the application of load and remove of load.
1 VIN x D IRMS = (1- D) x D x I OUT + xc / 12 f xL
2
2
, where D =
VOUT VIN
The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage. PWM MOSFET Selection In high current PWM application, the MOSFET power dissipation, package type and heatsink are the dominant design factors. The conduction loss is the only component of power dissipation for the lower MOSFET, since it turns on into near zero voltage. The upper MOSFET has conduction loss and switching loss. The gate charge losses are proportional to the switching frequency and are dissipated by the AIC1571. However, the gate charge increases the switching interval, tSW which increase the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance specifications.
L x IOUT L x IOUT , tFALL = . VIN - VOUT VOUT Where IOUT is transient load current step. tRISE =
In a typical 5V input, 2V output application, a 3H inductor has a 1A/S rise time, resulting in a 5S delay in responding to a 5A load current step. To optimize performance, different combinations of input and output voltage and expected loads may require different inductor value. A smaller value of inductor will improve the transient response at the expense of increase output ripple voltage and inductor core saturation rating.
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AIC1571
PUPPER = IOUT 2 x RDS(ON) x D + IOUT x VIN x tSW x f 2
conducting during the dead time between the turn off of the lower MOSFET and the turn on of the upper MOSFET. The diode's rated reverse breakdown voltage must be greater than twice the maximum input voltage. Linear Controller MOSFET Selection The power dissipated in a linear regulator is :
PLOWER = IOUT 2 x RDS(ON) x (1 - D)
The equations above do not model power loss due to the reverse recovery of the lower MOSFET's body diode. The RDS(ON) is different for the two previous equations even if the type devices is used for both. This is because the gate drive applied to the upper MOSFET is different than the lower MOSFET. Logic level MOSFETs should be selected based on on-resistance considerations, RDS(ON) should be chosen base on input and output voltage, allowable power dissipation and maximum required output current. Power dissipation should be calculated based primarily on required efficiency or allowable thermal dissipation. Rectifier Schottky diode is a clamp that prevent the loss parasitic MOSFET body diode from
PLINEAR = IOUT x (VIN2 - VOUT) Select a package and heatsink that maintains junction temperature below the maximum rating while operation at the highest expected ambient temperature.
Linear Output Capacitor The output capacitors for the linear controller provide dynamic load current. The linear controller uses dominant pole compensation integrated in the error amplifier and is insensitive to output capacitor selection. COUT2 and COUT3 should be selected for transient load regulation.
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AIC1571
APPLICATION CIRCUIT
C18 1000pF R15 10 VCC C16 2.2F 24 23 +3.3VIN VIN2 Q3 20N03HL VOUT3 1.5V C45-46 4 x 1000F + R11 1.87K R12 10K 12 22 15 21 PGND D5820 LGATE Q2 R4 5K 1 20 R2 OCSET 2.2K UGATE PHASE Q1 C15 1F L1 +5VIN +12VIN
+
1H C1-C7 6 x 1000F
GND
3.5H L2
VOUT1
+
C24-36 7 x 1000F
GATE3 FB3
16
19
VSEN C40 0.68F R8 2.2K
Q4 20N03HL
GATE2
13
18
FB1 R10 160K C42 R9 732K
VOUT2 1.8V C47-48 2 x 1000F +
R11 4.2K R12 10K
FB2
11
C41 10pF
17
COMP1
2.2nF
6 RT FAULT PGOOD SS C48 40nF 10 8 7 9 14 5 4 3 2
VID0 VID1 VID2 VID3 VID4
Circuit 1 Motherboard Power application Circuit
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AIC1571
C18 1000pF R2 2.2K 20 OCSET UGATE Q1 C15 1F +
+12VIN
R15 10
VCC C16 2.2F
L1 1H
C1-C7 6 x1000F
+5VIN
1
GND
24 23 +3.3VIN Q3 20N03H R11 VOUT3 1.5V C43-46 2 x 1000F 1.87K + R12 10K 19 VIN2 12 22 15
PHASE
3.5H L2 +
C24-36 7 x1000F
VOUT1
LGATE
Q2 R4 5K
GATE3
D5820
FB3
16
21
PGND
VSEN C40 0.68F R8 2.2K FB1 R9 732K
SS C48 40nF
9
18
C41 10pF
R10 160K C42
RT FAULT PGOOD VID0 VID1 VID2 VID3 VID4
10 17 8 7 13 6 5 4 3 2 14
COMP
2.2nF
GATE2
Q4 20N03HL
11
FB2 + R14 10K C47 1000F
VOUT2 1.27V
Circuit 2 Power Integration for 3-Output Power System
17
AIC1571
PHYSICAL DIMENSIONS
24 LEAD PLASTIC SO (300 mil) (unit: mm)
D
SYMBOL A A1
E H
MIN 2.35 0.10 0.33 0.23 15.20 7.40 10.00 0.40
MAX 2.65 0.30 0.51 0.32 15.60 7.60 10.65 1.27
B C D E
e
A
e
A1
1.27(TYP)
H
C L
B
L
18

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